(a) Field of the Invention
The present invention relates to a semiconductor device having a contact pad and, more particularly, to an improvement in the semiconductor device having the contact pad in contact with the source/drain regions. The present invention also relates to a method for manufacturing such a semiconductor device.
(b) Description of the Related Art
Along with development of finer patterns in a semiconductor device, the planar size of the semiconductor device has been remarkably reduced, and the thickness of the interlevel dielectric film has become larger. This results in an increase of the aspect ratio of contact holes used for receiving therein contact plugs in contact with the source/drain regions, and a reduction in an alignment margin during forming the contact holes. A smaller alignment margin makes it difficult to form the contact plug at a desired location of the source/drain regions.
In a memory device, such as a DRAM, a smaller size of memory cells reduces the pitch of gate electrodes, and accordingly reduces the area of the diffused region of the memory cell exposed from the gate electrodes.
Thus, there arises a problem that misalignment occurs in the semiconductor device between a contact hole having a smaller diameter and a corresponding diffused region of the memory cell, whereby a defective electric contact may occur in the semiconductor device.
As a countermeasure for solving the above problem, a self-alignment process is known wherein a contact pad to be in contact with an overlying contact plug and having a larger top surface is formed in self-alignment with the gate electrode for the diffused region, instead of embedding a conductive material in the contact hole to form the contact plug. This technique is described in JP-11(1999)-340436A.
The technique for forming the contact pad in self-alignment with the gate electrode uses a patterning step for patterning a conductive film on the semiconductor substrate to configure the contact pad, thereby facilitating formation of a suitable contact between the contact pad and the diffused region. In addition, the larger top surface of the contact pad increases an alignment margin during forming an overlying contact hole, thereby facilitating the connection between the contact pad and the overlying contact plug.
However, there is a problem in the above self-alignment technique that the peripheral area of the diffused region may be exposed from the contact pad due to misalignment of the mask pattern with respect to the source/drain diffused regions during patterning of the conductive material on the semiconductor substrate. This misalignment may cause, as shown in FIG. 6, occurring of a recess 25 in the diffused region 21 during the patterning to form the contact pad 22, wherein the recess 25 may divide the diffused region 21 formed on the semiconductor substrate 11.
The diffused region 21 and the substrate region of the semiconductor substrate 11 generally configure therebetween a p-n junction 31, across which a reverse bias voltage is applied for electric isolation during operation of the resultant semiconductor device. The recess 25 dividing the diffused region 21 may prevent a suitable reverse bias voltage from being applied across the p-n junction, causing an undesirable leakage current across the p-n junction. Thus, there may be a problem that the leakage current reduces the data retention time of the memory cell.